Field Programmable Gate Arrays (FPGAs) are popular for space application because of their low cost, reconfigurability, and low design turn around time. Triple modular redundancy (TMR) is a widely used design-hardening technique for obtaining high immunity against single event upsets (SEUs). As the name suggests, the circuit is triplicated and the final output is generated by taking the majority vote of those generated by the triplicates. The main disadvantage of TMR techniques known in the art is the excessive area overhead. While TMR is the most robust mitigation technique, the implementation of TMR greatly increases the overhead of the device and subsequently the area required for the circuitry. The hardened design can have up to 200% more area than the original circuit. In the context of space-based applications, this implies an increase of the payload by 200%.
Single event upsets are a major cause of concern for SRAM based FPGAs. Although SEUs show up as soft errors in combinational circuits, they transform into more serious permanent faults when they are mapped to FPGAs. The situation occurs because the same combinational circuits are mapped on the FPGA using Look Up Tables (LUTs), which consist of SRAM cells. As such, an SEU in these cells could be latched, thus transforming the transient fault into a permanent fault. Additionally, the interconnection of the FPGA is also controlled using the data stored in SRAM cells. Since the information defining the functionality of an FPGA is also stored in memory cells, an upset in them could lead to malfunctioning of the device and prove fatal to the mission. As such, it is critical that the SEUs be carefully addressed for a mission employing SRAM based FPGAs.
Design hardening is one of the techniques employed to mitigate SEUs. Hardening by design includes introducing hardware and/or software redundancy. Electronic devices intended for space applications can be designed from a library of SEU tolerant basic gates and memory cells. Such structures of gates and SRAM cells are known in the art. A SEU hardened version of a Boolean gate is obtained by modifying its basic structure by adding a few additional transistors. However, these SEU tolerant SRAM cells cannot be applied to programmable devices because the programmable devices are commercially off the shelf devices that are prefabricated. As such, the entire design cycle would need to be modified and it cost-prohibitive.
An alternative to using SEU hardened library of cells is to apply modular redundancy. Triple Modular Redundancy (TMR) is one such technique known in the art where a module is replicated three times and the output extracted from a majority voter as shown in FIG. 1, in which FIG. 1A illustrates the prior art TMR technique in block diagram form and FIG. 1B illustrates the prior art TMR technique at the gate level.
A TMR system can withstand only single upsets at any instant of time, thus, if two redundant modules are simultaneously upset, then the output cannot be guaranteed to be correct. Also, if two modules are permanently damaged, the whole TMR system has to be discarded. The redundant system is considered SEU tolerant under the assumption that the voter circuit is completely immune to SEUs.
The correct implementation of TMR depends on the type of module to be hardened. For example, the method of implementing TMR for sequential circuits differs from that of combinational circuits.
Field programmable gate arrays commonly known in the art include triple modular redundancy for SEU-hardening. While TMR is the most robust mitigation technique, the main drawback of using TMR for SRAM based FPGAs is that the voter circuit has to be implemented using SRAM cells which themselves are highly susceptible to upsets. Consequently, FPGAs are known in the art to include tri-state buffers, which can be used to effectively build an SEU tolerant voter circuit.
There remains a need in the art for a design-hardening technique with reduced overhead and area requirements over the circuit redundancy techniques known in the art.
However, in view of the prior art considered as a whole at the time the present invention was made, it was not obvious to those of ordinary skill in the pertinent art how the identified need could be fulfilled.